1 of 8 features ? 10 years minimum data retention in the absence of external power ? data is automatically protected during power loss ? unlimited write cycles ? low - power cmos operation ? read and write access times of 70 ns ? lithium energy s ource is electrically disconnected to retain freshness until power is applied for the first time ? full 10% v cc operating range (ds1265y) ? optional 5% v cc operating range (ds1265ab) ? optional industrial temperature range of - 40 c to +85 c, designated ind pin assignment pin description a0 - a19 - address inputs dq0 - dq7 - data in/data out ce - chip enable we - write enable oe - output enable v cc - power (+5v) gnd - ground nc - no connect description the ds1265 8m nonvolatile srams are 8,388,608 - bit, fully static nonvolatile srams organized as 1,048,576 words by 8 bits. each nv sram has a self - contained lithium energy s ource and control circuitry which constantly monitors v cc for an out - of - tolerance condition. when such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. t here is no limit on the number of write cycles which can be executed and no additional support circuitry is required for microprocessor interfacing. ds1265y/ab 8m nonvolatile sram 19 - 5616; rev 11/10 www.maxim - ic.com 13 1 2 3 4 5 6 7 8 9 10 11 12 14 35 36 - pin encapsulated package 740- mil extended a18 a14 a7 a6 a5 a4 a3 a2 a0 a1 v cc a19 nc a15 a17 we a13 a8 a9 a11 oe a10 dq7 ce 36 34 33 32 31 30 29 28 27 26 25 23 24 nc a16 a12 nc dq0 dq1 15 16 22 21 dq6 dq5 17 18 gnd dq2 dq3 dq4 19 20
ds1265y/ab 2 of 8 read mode the ds1265 devices execute a read cycle whenever we (write enable) is inact ive (high) and ce (chip enable) and oe (output enable) are active (low). the unique address specified by the 20 address inputs (a 0 - a 19 ) defines which of the 1,048,576 bytes of data is accessed. valid data will be available to the eight data output drivers within t acc (access time) after the last address input signal is stable, providing that ce and oe (output enable) access times are also satisfied. if oe and ce access times are not satisfied, then data access must be measured from the later - occurring signal ( ce or oe ) and the limiting parameter is either t co for ce or t oe for oe rather than t acc . write mode the ds1265 devices execute a write cycle whenever we and ce signals are active (low) after address inputs are stable. the later - occurring falling edge of ce or we will determine the start of the write cycle. the write cycle is terminated by the earlier rising edge of ce or we . all address inputs must be kept valid throughou t the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the oe control signal should be kept inactive (high) during write cycles to avoid bus con tention. however, if the output drivers are enabled ( ce and oe active) then we will disable the outputs in t odw from its falling edge. data retention mode the ds1265ab provides full functional capability for v cc greater than 4.75 volts and write protects by 4.5 volts. the ds1265y provides full functional capability for v cc greater than 4.5 volts and write protects by 4.25 volts. data is maintained in the absence of v cc without any additional su pport circuitry. the nonvolatile static rams constantly monitor v cc . should the supply voltage decay, the nv srams automatically write protect themselves, all inputs become don?t care, and all outputs become high - impedance. as v cc falls below approximatel y 3.0 volts, a power switching circuit connects the lithium energy source to ram to retain data. during power - up, when v cc rises above approximately 3.0 volts, the power switching circuit connects external v cc to ram and disconnects the lithium energy sou rce. normal ram operation can resume after v cc exceeds 4.75 volts for the ds1265ab and 4.5 volts for the ds1265y. freshness seal each ds1265 device is shipped from dallas semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level greater than v tp , the lithium energy source is enabled for battery backup operation.
ds1265y/ab 3 of 8 absolute maximum ratings voltage on any pin relative to ground - 0.3v to +6.0v operating temperature range commercial: 0c to + 70c industrial: - 40c to +85c storage temperature - 40c to +85 c lead temperature (soldering, 10 s ) +260 c note: edip is wave or hand soldered only. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions ( t a : see note 10 ) parameter symbol min typ max units notes ds1265ab power supply voltage v cc 4.75 5.0 5.25 v ds1265y power supply voltage v cc 4. 5 5.0 5.5 v logic 1 input voltage v ih 2.2 v cc v logic 0 input voltage v il 0 +0.8 v dc electrical c har ac te r is tic s (v cc =5v 5% for ds1265ab) ( t a : see note 10 ) (v cc =5v 10% for ds1265y) parameter symbol min typ max units notes input leakage current i il - 2.0 +2.0 a i/o leakage current i io - 2.0 +2.0 a output current @ 2.4v i oh - 1.0 ma output current @ 0.4v i ol 2.0 ma standby current ce =2.2v i ccs1 1.0 1.5 ma standby current ce =v cc - 0.5v i ccs2 100 200 a operating current i cco1 85 ma write protection voltage (ds1265ab) v tp 4.50 4.62 4.75 v write protection voltage (ds1265y) v tp 4.25 4.37 4.5 v capacitance ( t a = + 25 c) parameter symbol min typ max units notes input capacitance c in 10 20 pf output capacitance c i/o 10 20 pf
ds1265y/ab 4 of 8 ac electrical c har ac te r is tic s (v cc =5v 5% for ds1265ab) ( t a : see note 10 ) (v cc =5v 10% for ds1265y) parameter symbol ds1265ab - 70 ds1265y - 70 units notes min max read cycle time t rc 70 ns access time t acc 70 ns oe to output valid t oe 35 ns ce to output valid t co 70 ns oe or ce to output active t coe 5 ns 5 output high z from deselection t od 25 ns 5 output hold from address change t oh 5 ns write cycle time t wc 70 ns write pulse width t wp 55 ns 3 address setup time t aw 0 ns write recovery time t wr1 t wr2 5 15 ns ns 12 13 output high z from we t odw 25 ns 5 output active from we t oew 5 ns 5 d ata setup time t ds 30 ns 4 data hold time t dh1 t dh2 0 10 ns ns 12 13 timing diagram: read cycle see note 1
ds1265y/ab 5 of 8 timing diagram: write cycle 1 timing diagram: write cycle 2 see notes 2, 3 , 4, 6, 7, 8 and 13
ds1265y/ab 6 of 8 power - down/power - up condition see note 11 power - down/power - up timing ( t a : see note 10) parameter symbol min typ max units notes v cc fail detect to ce and we inactive t pd 1.5 s 11 v cc slew from v tp to 0v t f 150 s v cc slew from 0v to v tp t r 150 s v cc valid to ce and we inactive t pu 2 ms v cc valid to end of write protection t rec 125 ms ( t a = + 25 c) parameter symbol min typ max units notes expected data retention time t dr 10 years 9 warning: under no circumstance are nega tive undershoots, of any amplitude, allowed when device is in battery backup mode. notes: 1. we is high for a read cycle. 2. oe = v ih or v il . if oe = v ih during write cycle, the output buffers rema in in a high - impedance state. 3. t wp is specified as the logical and of ce or we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t ds is measured from the earlier of ce or we going high. 5. these parameters are sampled with a 5 pf load and are not 100% tested. 6. if the ce low trans ition occurs simultaneously with or latter than the we low transition, the output buffers remain in a high - impedance state during this period. 7. if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in high - impedance state during this period.
ds1265y/ab 7 of 8 8. if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high - impedance state during this period. 9. each ds1265 has a built - in switch that disconnects the lithium source until the user first applies v cc . the expected t dr is defined as accumulative time in the absen ce of v cc starting from the time power is first applied by the user. this parameter is assured by component selection, process control, and design. it is not measured directly during production testing. 10. all ac and dc electrical characteristics are valid o ver the full operating temperature range. for commercial products, this range is 0 c to 70 c. for industrial products (ind), this range is - 40 c to +85 c. 11. in a power - down condition the voltage on any pin may not exceed the voltage on v cc . 12. t wr1 and t dh1 are measured from we going high. 13. t wr2 and t dh2 are measured f rom ce going high. 14. ds1265 modules are recognized by underwriters laborator ies (u l ) under file e99151. dc test conditions ac test conditions outputs open output load: 100 pf + 1ttl gate cycle = 200ns for operating current input pulse levels: 0v to 3.0v all voltages are referenced to ground timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5 ns ordering information part temp ra nge supply tolerance pin - package speed grade (ns) ds1265ab - 70+ 0c to +70c 5v 5% 36 740 edip 70 ds1265ab - 70ind+ - 40c to +85c 5v 5% 36 740 edip 70 ds1265y - 70+ 0c to +70c 5v 10% 36 740 edip 70 ds1265y - 70ind+ - 40c to +85c 5v 10% 36 740 edip 70 + denotes a lead (pb) - free/rohs - compliant p ackage. package information for the latest package outline information and land patterns, go to www.maxim - ic.com/p ackage . note that a ?+?, ?#?, or ? - ? in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status . s package type package code outline no. land pattern no. 36 edip mdt36+1 ? 21- 0245
ds1265y/ab 8 of 8 revision history revision date description pages changed 11/10 u pdated the storage information, soldering temperature, and lead temperature information in the absolute maximum ratings section; removed the - 10 0 min/max information from the ac electrical characteristics table; updated the ordering information table (remo ved - 10 0 parts and leaded - 7 0 parts); replaced the package outline drawing with the package information table 1, 3, 4, 7
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